`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   10:41:26 11/29/2012
// Design Name:   MEM_WR
// Module Name:   D:/Workspace/xilinx workspace/HFM_DETECTOR/mem_wr_simu.v
// Project Name:  HFM_DETECTOR
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MEM_WR
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module mem_wr_simu;

	// Inputs
	reg clk;
	reg rst;
	reg [15:0] in_r;
	reg [15:0] in_i;

	// Outputs
	wire [15:0] out_r;
	wire [15:0] out_i;
	wire [7:0] addr;
	wire wr_en;
	integer i;
	always #10 clk = ~clk;
	// Instantiate the Unit Under Test (UUT)
	MEM_WR uut (
		.clk(clk), 
		.rst(rst), 
		.in_r(in_r), 
		.in_i(in_i), 
		.out_r(out_r), 
		.out_i(out_i), 
		.addr(addr), 
		.wr_en(wr_en)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		in_r = 0;
		in_i = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		rst = 1;
        
		// Add stimulus here
		for(i=0;i<500;i=i+1)
			#20 
			begin
			in_r = i;
			in_i = 1;
			end

	end
      
endmodule

